A conventional semiconductor device is now explained using FIG. 16 which is a cross-sectional diagram showing substantial parts of the semiconductor device. A 2-in-1 semiconductor module 500 is shown in FIG. 16 as an example of the semiconductor device. In the diagram, reference numeral 101 represents a heat dissipation metal base plate. Reference numeral 102 represents an insulating substrate with conductive patterns (ceramic insulating substrate) that is placed on and joined to the metal base plate 101 by solder 103. This insulating substrate with conductive patterns (ceramic insulating substrate) 102 is formed by laminating a conductive pattern 102b on a front surface of an insulating substrate (ceramic substrate) 102a and a back-surface conductive film 102c on a rear surface of the same (i.e., the metal patterns 102b and 102c are laminated on the front and rear surfaces of the insulating substrate 102a). Reference numeral 104 represents semiconductor chips (semiconductor power chips) that are mounted on the conductive pattern 102b of the insulating substrate with conductive patterns 102 by solder 105. Reference numeral 106 represents a resin case for accommodating a cooling base (the metal base plate) 101 that is joined to the back-surface conductive film 102c of the insulating substrate with conductive patterns (ceramic insulating substrate) 102 by the solder 103. Reference numeral 107 represents metal bar terminals, which are external lead terminals, joined to the conductive pattern 102b by the solder 105. Bonding wires 108 are used to join the semiconductor chips 104 to each other or one of the semiconductor chips 104 to the conductive pattern 102b in another area.
Patent Document 1 discloses a semiconductor device in which semiconductor chips are disposed on an insulating substrate with conductive patterns, and a plurality of metal pins that is fixed to the semiconductor chips and the conductive patterns are fixed to a printed circuit board. In this semiconductor device, wiring inductances can be reduced by disposing metal foil pieces, which are laminated on the front and rear surfaces of this printed circuit board, in such a manner as to face each other in this printed circuit board.
Patent Documents 2 and 3, on the other hand, each describe that wiring inductances can be reduced by disposing positive-electrode and negative-electrode external lead terminals of the semiconductor device in parallel.
Patent Document 1: Japanese Patent Application Publication No. 2009-64852 (paragraphs 0132 to 0134, and FIG. 17)
Patent Document 2: Japanese Patent Application Publication No. 2001-274322
Patent Document 3: Japanese Patent Application Publication No. 2004-214452
A semiconductor device is required to be able to reduce wiring inductances generated therein, in order to reduce a surge voltage that is generated upon the switching operation or an outside voltage surge.
Unfortunately, it is difficult for the semiconductor device shown in FIG. 16 to realize low inductances, considering the combinations of the wiring inductances of the insulating substrate with conductive patterns, the bonding wires, the external lead terminals, and the like.
Moreover, Patent Documents 1, 2 and 3 do not mention that the reduction of the wiring inductances and the sizes of the semiconductor devices can be realized by a combination of the structure in which the metal foil pieces on the front and rear surfaces of the printed circuit board with metal pins are disposed on the semiconductor chips in such a manner as to face each other, and the configuration in which the external lead terminals (P-terminal and N-terminal, U-terminal and P-terminal or N-terminal, etc.) formed from metal bars are disposed adjacent to each other in parallel.
According to Patent Document 1, the metal foil pieces on the front and rear surfaces of the printed circuit board face each other in the printed circuit board but are not aligned with the positions of the semiconductor chips, and the external lead terminals are connected to the misaligned positions, which increases the size of the printed circuit board, and hence the size of the semiconductor device. In addition, connecting the external lead terminals to the printed circuit board weakens the mechanical strengths of these connecting parts.